The present invention relates to a semiconductor integrated circuit device and, more particularly, to a technique which is effective if applied to a device including a memory mat section where dynamic memory cells are arranged in a matrix and an input/output circuit connected with external terminals.
A dynamic RAM, in which the threshold voltage of MOSFETs contained therein is optimized by a triple-well structure, is proposed in "Nikkei Micro Device", pp. 54 to 58, issued in March, 1989, NIKKEI McGRAW-HILL. In this dynamic RAM, the memory cells formed on an N-substrate have their soft error resistance improved by making use of the P-type well and the N-type substrate junction, and data breakage, which might be caused by the undershoot of input pins or by the minority carriers produced from the N-channel MOSFETs of the peripheral circuits, is eliminated to improve their data protecting characteristics.
Specifically, there is disclosed a technique of applying V.sub.BB to the P-well of memory mats, as in the prior art, and V.sub.SS to the P-well formed with an n-type peripheral circuit and an input protect circuit.
In the aforementioned triple well structure, in order to solve the problem of the substrate effect resulting from the finer structure of the elements and the drop of the power supply voltage, the well region, in which there are formed the P-channel MOSFETs and the N-channel MOSFETs constituting the peripheral circuits, is fed with a bias voltage which characteristically optimizes the threshold voltage. On the other hand, the P-type well region of the memory array is fed with a back bias voltage, as in the prior art.
Japanese Patent Laid-Open No. 267617/1993 discloses a technique wherein, taking the refresh characteristics of memory cells into consideration, the ground potential is provided through a resistor to the P-well where the memory cells are formed and directly to the P-well where the peripheral circuits are formed.
Japanese Patent Laid-Open No. 276673/1991 discloses a technique wherein the absolute value of the well potential of the P-well, in which the N-MOS transistors included in peripheral circuits other than sense amplifiers are formed, is set higher (or deeper) than that of the well potential of the P-well where the N-MOS transistors of the sense amplifiers are formed; and the absolute value of the well potential of the P-well where the N-MOS transistors included in the sense amplifiers are formed is set higher (or deeper) than that of the well potential of the P-well where the N-MOSs included in the memory cells are formed.
Japanese Patent Laid-Open No. 83289/1991 discloses a technique for setting the threshold value of MOS transistors constituting the memory cells higher than that of the MOS transistors constituting the peripheral circuits.
Japanese Patent Laid-Open No. 212453/1992 discloses a technique for setting the well potential of the P-well for the peripheral circuit section, including a data input buffer and a data output buffer to the ground potential and setting the well potential of the P-well for the memory cell array to a negative potential or the ground potential.
Japanese Patent Laid-Open No. 317372/1992 discloses two techniques: one is a technique for setting the well potential of the P-well of the memory cell matrix region to an internal voltage, setting the well potential of the P-well where N-MOS transistors included in the peripheral circuits are formed to the ground potential and setting the well potential, of the P-well where N-MOSs for the output buffer are formed to the ground potential; the other is a technique for setting the well potential of the P-well of the memory cell matrix region to an internal voltage, setting the well potential of the P-well where the N-MOS transistors included in the peripheral circuits are formed to the ground potential, and setting the well potential of the P-well where an N-type impurity diffusion layer of the input protective device is formed to an internal voltage.
Japanese Patent Laid-Open No. 119958/1987 discloses two techniques: one is a technique for applying 0V to the P-well where the N-MOS transistors included in the memory cell array are formed, and applying -3V to the P-well where the N-MOS transistors included in the peripheral circuits are formed; the other is a technique for applying 0V to the P-well where the N-MOSs included in the memory cell array are formed and applying -3V to the P-well where the N-MOSs included in the input circuit and the input protective circuit are formed.